1. Field of the Invention
The present invention relates to a semiconductor memory device, a memory test method and a computer program for a designing method of a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device and a memory test method for use in inspecting a plurality of macros by a self-test circuit, and a computer program for a designing method of the semiconductor memory device.
2. Description of Related Art
In the field of a semiconductor integrated circuit, a high-speed test is being increasingly demanded and required in order to address an increase of the degree of integration in accordance with finer processes, an increase of the capacity of built-in memory owing to higher functionality, and an increase of a test time owing to the improvement of test quality and other reasons.
Japanese Patent Publication No. JP2000-156078A discloses a semiconductor storage device having a function of writing data read from a specific bank into another bank, capable of reducing a data write time for a test, and having a multibank structure suitable for application to a synchronous DRAM or others. The semiconductor storage device having a multibank structure includes: a bank-to-bank data copy control circuit that specifies any one of a plurality of memory banks as a source bank based on a command for specifying a data copy mode between banks and performs control for writing data read from the source bank into at least one of the other memory banks.
Japanese Patent Publication No. JP2004-178676A discloses a semiconductor integrated circuit capable of suppressing an increase in gate scale required for inspecting a memory macro cell, performing inspection at a high operation frequency, and also reducing power consumption at the time of simultaneous inspection. The semiconductor integrated circuit has incorporated therein a plurality of memory macro cells with write data, an address and an access signal being taken as inputs and read data being taken as an output, determines the quality of the plurality of memory macro cells through write and read operations, and performs self inspection in terms of electric characteristics based on the quality determination. The semiconductor integrated circuit includes: the plurality of memory macro cells; a write data signal generating unit that generates the write data in any memory macro cell of the plurality of memory macro cells; and a data comparing unit that compares the write data and the read data of any memory macro cell of the plurality of memory macro cells. A read data output pin of any memory macro cell of the plurality of memory macro cells and a write data input pin of any memory macro cell other than the above-mentioned memory macro cell are sequentially connected together, the plurality of memory macro cells are connected in series. The write data signal generating unit, the plurality of memory macro cells, and the data comparing unit are connected in series. Based on the comparing result from the data comparing unit, the quality of the plurality of memory macro cells is determined.
Japanese Patent Publication No. JP-A-Heisei 10-83699 (corresponding to U.S. Pat. No. 5,923,599 (A)) discloses a memory device capable of inspecting a selected portion. The memory device includes: a semiconductor memory array; a component related thereto; and a self-inspection device including a device for inspecting the memory array and the related component and inspecting a selected sub-array of the semiconductor memory array.
Japanese Patent Publication No. JP-A-Heisei 10-187554 (corresponding to U.S. Pat. No. 5,946,246 (A)) discloses a semiconductor memory device having a self-test circuit capable of simultaneously testing many RAMs by sharing one controller for testing the built-in RAMs with varied sizes to minimize interconnection. The semiconductor memory device having a self-test circuit includes: a plurality of memory blocks; a plurality of selecting means adapted to select an address, a control signal, and data of the plurality of memory blocks as normal/test in response to a test mode signal; a plurality of background generating means that generates comparison data for comparison with data to be written in the plurality of memory blocks; a plurality of comparing means that compares the comparison data with the data read from the plurality of memory blocks in response to the test mode signal and outputs the comparison result; combining means that combines respective outputs from the plurality of comparing means to generate a test result, and test control means that provides a test address and a control signal to the plurality of selecting means, provides a background number and an output inverse control signal to the plurality of background generating means, and provides a comparison control signal to the plurality of comparing means, in response to the test mode signal.
Japanese Patent Publication No. JP-A-Heisei 11-45596 discloses a semiconductor integrated circuit capable of reliably performing a test with a simple circuit even when a plurality of built-in semiconductor storage circuits has varied storage capacities. The semiconductor integrated circuit includes: a plurality of semiconductor storage circuits with varied storage capacities; and a test circuit that performs an operation test for a plurality of semiconductor storage circuits. The test circuit includes: data signal generating means that generates data for writing data in the semiconductor storage circuit, expected-value data generating means that generates expected-value data; expected-data matching means that reads data from a data-written semiconductor storage circuit and determines whether the read data matches the data outputted from the expected-value data generating means; detecting means that detects a selection state of a specific word line of each of the semiconductor storage circuits; and an address signal generating unit that generates an address signal according to each of the semiconductor storage circuits based on a detection signal from the detecting means.
We have now discovered the following facts. FIGS. 1A and 1B show a known memory test circuit described in JP-A-Heisei 10-187554. The memory test circuit includes: a plurality of RAM blocks R31, R32, and R33; test control means (test control circuit 3100); and combining means G31. In this conventional technique, by way of example, the number of RAM blocks as a plurality of memory blocks is three. Hereinafter, each of the plurality of RAM blocks R31, R32, and R33 is represented as a RAM block R3n (n is 1, 2, or 3). The RAM block R3n includes a RAM macro RAM3n, a selection circuit MUX3n, a background circuit BG3n, and a comparator COMP3n. The selection circuit MUX3n selects an address, a control signal, and data of the RAM macro RAM3n as normal or test in response to a BISTMODE (Built-In-Self-Test MODE) signal 3500. The background circuit BG3n generates data to be written in the RAM macro RAM3n and data for comparison. The comparator COMP3n compares the comparison data with data read from the RAM macro RAM3n in response to the BISTMODE signal 3500, and outputs the comparison result. The test control means provides a test address tA and a test write control signal tWEN to the plurality of selection circuits MUX31, MUX32, and MUX33, and provides a test enable control signal tENn to the plurality of selection circuits MUX3n, in response to the BISTMODE signal 3500. The test control means further provides a background number BGN and an output inverse control signal INVBG to a plurality of background circuits BG31, BG32, and BG33, and provides a comparison control signal COMPARE to a plurality of comparators COMP31, COMP32, and COMP33. The combining means G31 performs logical OR on error signals from the plurality of comparators COMP31, COMP32, and COMP33 to generate the test result.
In an operation of the above-described memory test circuit, upon receiving the BISTMODE signal 3500, the test control circuit 3100 first generates a test address tA, a test write control signal tWEN, an output inverse control signal INVBG, a comparison control signal COMPARE, and a background number BGN. Then, upon receiving the background number BGN and the output inverse control signal INVBG, the background circuit BG3n generates write data tD3n and comparison data tC3n. Upon receiving the BISTMODE signal 3500, the selection circuit MUX3n supplies the test address tA, the test write control signal tWEN, the test enable control signal tEN, and write data tD3n to the RAM macro RAM3n. The RAM macro RAM3n performs a write operation and a read operation. The comparator COMP3n compares output data rD3n from the RAM macro RAM3n and comparison data cD3n. The combining means G31 combines the comparison results from the comparators COMP31, COMP32, and COMP33 to output an ERROR signal 3600.
In this technique, there is no function of controlling each test at each RAM block R3n, and the plurality of RAM blocks are simultaneously tested for reducing the testing time. Therefore, compared with the case of a normal operation in which an LSI implemented on a product performs an operation as an original LSI function (hereinafter simply referred to as a normal operation), a voltage drop in the test is increased. This prevents a test at an operating frequency of the normal operation, thereby causing an outflow of defective products not satisfying the operating frequency. One reason for this is as follows. LSI designing is performed with a power-supply impedance targeted for an operation current at the time of normal operation. However, at the time of the operation of the memory test circuit, all RAM blocks simultaneously operate, and therefore an operation current larger than that at the time of the normal operation flows to cause a voltage drop.
It is desired that a technique for preventing the occurrence of characteristic deterioration at the time of testing a plurality of RAM macros.